Design & Reuse
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167 IP
101
0.0
AHB Lite to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and the...
102
0.0
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...
103
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
104
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AHB Multilayer Interconnect IP
SmartDV’s AHB Multilayer Interconnect IP is a silicon-proven, high-throughput solution designed to manage complex on-chip communication in SoC designs...
105
0.0
AHB Performance Subsystem - ARM Cortex M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
106
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AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
107
0.0
AHB Secure Subsystem - ARM Cortex M3
The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It in...
108
0.0
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured...
109
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AHB Slave to SPI Master
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...
110
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AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
111
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AHB to APB Bridge
The AHB to APB bridge is an AHB slave, providing an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are...
112
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AHB To APB Bridge IP
SmartDV’s AHB to APB Bridge IP is a high-performance solution that enables seamless communication between the high-speed AMBA AHB bus and the low-powe...
113
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AHB to APB Bus Bridge
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction. This is accomplished via two small state machines ...
114
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AHB to AXI Bridge IP
SmartDV’s AHB to AXI Bridge IP Core provides a seamless interface between AMBA AHB and AXI protocols, enabling smooth integration of legacy AHB-based ...
115
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AHB-Lite to AHB-Lite Asynchronous Bridge
The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...
116
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Bi-directional AMBA AHB/AHB bridge
The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any fre...
117
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Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....
118
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Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...
119
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TileLink To AHB Bridge IP
TileLink to AHB Bridge IP core is compliant with SiFive Tilelink and AMBA AHB Specification. Through its compatibility,it provides a simple interface ...
120
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TileLink To APB Bridge IP
Tilelink2apb Bridge IP core is compliant with SiFive Tilelink and AMBA APB Specification. Through its compatibility, it provides a simple interface to...
121
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BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
122
0.0
Elliptic Curve Cryptography (ECC) core with AMBA APB interface
The GRECC core implements Elliptic Curve Cryptography (ECC) which is used as a public key mechanism and is well suited for application in mobile commu...
123
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Smart Network-on-Chip (NoC) IP
AI-Enhanced Automation for Smarter SoC Design FlexGen™ by Arteris redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge...
124
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AMBA AHB Address Trapper
The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order...
125
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AMBA AHB Simple Master Bridge
The Veriest AMBA AHB Simple Master Bridge Design IP provides a bridge between the embedded AMBA AHB bus master and a simplified generic local bus. The...
126
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AMBA AHB Slave to Local Interface Bridge
The Veriest AMBA AHB Slave Bridge Design IP offers a simple solution to provide a bridge between the embedded AMBA AHB bus and a simplified generic lo...
127
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AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
128
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AMBA AXI Data Prefetch Buffer
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM...
129
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AMBA AXI Data Writer Spreader
The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data ma...
130
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AMBA AXI Performance Monitor
The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility ...
131
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AMBA interface for Actel MIL-STD-1553B Cores
The GR1553 is a set of AMBA AHB/APB wrappers for the Actel AX/RTAX MIL-STD-1553B cores. Wrappers for the following Actel cores are provided: Core1553B...
132
0.0
ONFI 2.3 NAND Flash Controller
The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...
133
0.0
Uni-directional AMBA AHB to AHB bridge
The Uni-directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected...
134
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Internal Synchronous SRAM Controller Core
The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...
135
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Spacewire Codec with AHB host interface
The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol id...
136
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APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
137
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APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB sla...
138
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APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...
139
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APB Multilayer Interconnect IP
SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...
140
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APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S...
141
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APB Subsystem
The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...
142
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APB to AHB Bridge IP
SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...
143
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APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...
144
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APB to AXI Bridge IP
SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...
145
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APB UART with optional ISO7816-3
The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard ...
146
0.0
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
147
0.0
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
148
0.0
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
149
0.0
SPI Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
150
0.0
SPI to AHB - Lite Bridge
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...